A Multidimensional Configurable Processor Array - Vocalise

نویسندگان

  • Jiang Li
  • Yusuke Atsumari
  • Hiromasa Kubo
  • Yuichi Ogishima
  • Satoru Yokota
  • Hakaru Tamukoh
  • Masatoshi Sekine
چکیده

SUMMARY A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Configurable Soft Processor Arrays Using the OpenFire Processor

Single-chip multiprocessor systems, while requiring significantly less design effort than custom hardware solutions, fall behind custom RTL in performance. In an effort to decrease this performance gap, the individual processors in an array can be tailored to their specific application. In this paper we present the OpenFire, a Xilinx MicroBlaze-compatible processor designed for configurable arr...

متن کامل

Low-Power Configurable Processor Array for DLMS Adaptive Filtering

I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is...

متن کامل

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable swi...

متن کامل

Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)

In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...

متن کامل

Designing A Re-Configurable Fractional Fourier Transform Architecture Using Systolic Array

FRFT (Fractional Fourier Transforms) algorithm, which has been derived from DFT, computes the angular domains within the time and frequency domains. This algorithm is increasingly used in the field of signal filtering, quantum mechanics and optical physics. In this paper we develop an efficient, systolic, reconfigurable architecture for a particular type of FRFT called MA-CDFRFT (Multi Angle Ce...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEICE Transactions

دوره 98-D  شماره 

صفحات  -

تاریخ انتشار 2015